1. Field of the Invention
This invention relates generally to a nonvolatile memory element and, more specifically, to a transistor-type ferroelectric nonvolatile memory element by using a ferroelectric material as a control gate.
2. Prior Art
A ferroelectric memory which has now been put into practice has a constitution in which the capacitor of DRAM is replaced by a ferroelectric capacitor (see, for example, Japanese Unexamined Patent Publication (Kokai) No. 113496/1990). The operation is based upon the detection of a difference in the amount of electric charge between when the polarization of capacitance of the ferroelectric material is inverted and when it is not inverted, thereby to judge whether the stored data is [1] or [0]. Therefore, this could become a so-called destructive readout in which the data held at the time of reading out the data is destroyed.
According to this method in which an electric charge by the inversion of polarization is taken out and detected as a current directly, further, the area of the capacitance becomes small and the current value becomes small so will not to be detected. This is a fundamental problem that occurs since the memory of this structure does not comply with the scaling side like the DRAM. Namely, there is a limitation on decreasing the area, electric current and electric power used therefor.
On the other hand, a field-effect transistor (FET) ferroelectric memory that uses a ferroelectric material as a control gate, works to turn a channel between source and drain on and off as the polarization of the ferroelectric material induces the electric charge of the channel of the transistor. In this case, the rate of change in the drain current remains the same despite the cell area is contracted proportionally. This means that the memory cell of the ferroelectric transistor complies with the scaling rule (Journal of the Japanese Academy of Electronic Information Communication, 77-9, 1994, pp. 976). In principle, therefore, there exists no limitation on decreasing he sizes.
Further, the transistor-type ferroelectric memory maintains the FET turned on or off relying upon the polarization of the ferroelectric material, and does not permit the data to be destroyed by the reading operation on a low voltage. Namely, the nondestructive readout can be accomplished.
The field-effect ferroelectric memory transistors using a ferroelectric material as a control gate can be roughly divided into two kinds. One kind is a ferroelectric transistor having an MFIS (metal-ferroelectric-insulator-semiconductor) structure in which the ferroelectric material undergoes the polarization to induce an electric charge on the surface of the semiconductor substrate via a gate-insulating film.
The other kind is a ferroelectric transistor having a gate of an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure, and in which a metal (M) layer is sandwiched between a ferroelectric layer and an insulating layer of the MFIS structure. The present invention is concerned with the latter MFMIS.
The metal layer or the M layer referred to in this specification stands for a metal layer as well as a conductor layer such as of polycrystalline silicon.
FIG. 12 is a sectional view illustrating, in a simplified manner, the principle of a conventional MFMIS ferroelectric memory (T. Nakamura et al., Dig. Tech. Pap. of 1995 IEEE Int. Solid State Circuits Conf. p. 68, 1995). In FIG. 12, a source region 82 and a drain region 83 are formed in the main surface of a semiconductor substrate (S) 80, and a gate-insulating layer (I) 81 is laminated on the main surface of the semiconductor substrate therebetween. A first electrically conducting film (M) 84, a ferroelectric layer (F) 85 and a second electrically conducting film (M) 86 are stacked on the gate-insulating layer 81.
FIG. 13 shows an equivalent circuit of an MFMIS-structure portion of FIG. 12. In FIG. 13, it is necessary, from the standpoint of holding the memory, to apply a voltage until the polarization of the ferroelectric material F is saturated to a sufficient degree in polarizing the ferroelectric layer F by applying a voltage across the upper electrode A and the semiconductor substrate B. For this purpose, it is important to so design that a capacitance CF (capacitance of the ferroelectric layer) is smaller than a capacitance CI (capacitance of the gate-insulating layer). The capacitances CF and CI vary in proportion to the effective surface area of the gate-insulating layer I or the ferroelectric layer F to which a voltage is applied, and vary in reverse proportion to the thickness thereof.
It can therefore be contrived to decrease the thickness of the gate insulating layer I and to increase the thickness of the ferroelectric layer F, so that the capacitance CF (capacitance of the ferroelectric layer) becomes smaller than the capacitance CI (capacitance of the gate-insulating layer). Limitation, however, is imposed on decreasing the thickness of the gate-insulating layer I from the standpoint of breakdown voltage and leakage current. When the thickness of the ferroelectric layer F is increased, a high polarization voltage is necessary for saturating the polarization of the ferroelectric material.
The conventional method of selecting the capacitance CF to be smaller than the capacitance CI by avoiding these problems, is to vary the effective areas of the capacitances CF and CI. FIG. 14 is a diagram illustrating the principle in a simplified manner. It can be considered that FIG. 14 is a plan view of when the structure of FIG. 12 is seen from the upper side. An MFMIS structure 92 having a ferroelectric layer is formed in only a portion of the area of the MIS (metal-insulator-semiconductor) portion 91 that constitutes CI. Reference numeral 80 denotes a semiconductor substrate, 82 denotes a source region, and 83 denotes a drain region. The above conventional method makes it possible to design the capacitance CF to be smaller than the capacitance CI as required.
The above conventional method, however, involves a problem in that despite the MFMIS portion 92 is formed in a minimum machinable size, the MIS portion 91 becomes larger by an area ratio relative to the MFMIS portion 92 and, after all, occupies a large area making it difficult to accomplish a high degree of integration. Another problem of the conventional structure shown in FIG. 12 is that it is difficult to shorten the channel length between source and drain to a sufficient degree maintaining good reproduceability while adjusting the positions of source, drain and gate.
That is, as shown in FIG. 12, if the MFMI portion is formed in the same size and, then, the heat treatment is effected to introduce impurities for forming source and drain, impurities contained in the ferroelectric material are likely to be liberated and may diffuse into silicon to deteriorate the device characteristics. Further, when the end surface is machined at one time as shown in FIG. 12, the leakage current may increase on the side walls.
On the other hand, if the MIS structure is formed by using polycrystalline silicon on a silicon oxide film by employing a self-alignment method by using a silicon gate and if the MFM (metal-ferroelectric-metal) structure is constituted after the diffusion of silicon gate, then, the channel length can be decreased between source and drain. In this case, however, very little margin is allowed for positioning in constituting the MFM structure on the MIS structure.
That is, referring to FIG. 15, if an electrically conductor 84 of a ferroelectric material (F) 85 is connected via a contact hole 89 formed in an interlayer-insulating film 88 on the upper part of a silicon gate transistor having a polycrystalline silicon gate 87, then, the electrically conductor 84 comes into contact with the silicon substrate 80 as shown in FIG. 16 due to deviation in the positioning of the contact hole 89. Therefore, the gate width of the silicon gate 87 cannot be decreased to a sufficient degree by taking into consideration the positioning precision of the contact hole 89.